1、在软件中输入代码
module Register_File#(parameter word_size=32,addr_size=5)
(output [word_size-1:0] Data_Out_1,Date_Out_Out_2,
input [word_size-1:0] Data_in,
input [addr_size-1:0] Read_Addr_1, Read_Addr_2, Write_Addr,
input Write_Enable,Clock);
reg [word_size-1: 0] Reg_File [31: 0]; //32bit x32 word memory declaration

assign   Data_Out_1=Reg_File[Read_Addr_1];
assign   Date_Out_Out_2=Reg_File[Read_Addr_2];

always @ (posedge Clock) begin
if  (Write_Enable == 1'b1) 
Reg_File [Write_Addr]<=Data_in;
end

endmodule
2、输入测试代码
`timescale 1 ps/ 1 ps
module Register_File_vlg_tst();

reg Clock;
reg [31:0] Data_in;
reg [4:0] Read_Addr_1;
reg [4:0] Read_Addr_2;
reg [4:0] Write_Addr;
reg Write_Enable;

wire [31:0] Data_Out_1;
wire [31:0] Date_Out_Out_2;

Register_File i1 (

.Clock(Clock),
.Data_Out_1(Dat