`timescale 1ns / 1ps 
//同步复位 异步释放  并且将输出的信号转换成高电平有效
module reset(
    input        clk  ,
    input        rst_n,
    output       reset
    );
reg    reset1;
reg    reset2;


always @(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
    reset1<=1'b1;
    reset2<=1'b1;
    end
    else begin
    reset1<=(~rst_n);
    reset2<=reset1  ;
    end
end
assign reset=reset2;  
endmodule

一个语句块对多个reg赋值的时候用begin end嵌套