1Alwaysblock1

两种方法实现与门

// synthesis verilog_input_version verilog_2001
module top_module(
    input a, 
    input b,
    output wire out_assign,
    output reg out_alwaysblock
);
	assign out_assign = a & b;
    always@(*)
        out_alwaysblock <= a&b;
endmodule

2Alwaysblock2

异或门

module top_module(
    input clk,
    input a,
    input b,
    output wire out_assign,
    output reg out_always_comb,
    output reg out_always_ff   );
	assign out_assign = a ^ b;
    always@(*)
        out_always_comb <= a ^ b;
    always@(posedge clk)
        out_always_ff <= a ^ b;
endmodule

3Always if

module top_module(
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output wire out_assign,
    output reg out_always   ); 
    assign out_assign = (sel_b1 & sel_b2) ? b : a;
	always @(*) begin
        if (sel_b1 & sel_b2) begin
            out_always <= b;
        end
        else begin
            out_always <= a;
        end
    end
endmodule

4Always if2

module top_module (
    input      cpu_overheated,
    output reg shut_off_computer,
    input      arrived,
    input      gas_tank_empty,
    output reg keep_driving  ); //

    always @(*) begin
        if (cpu_overheated)
           shut_off_computer = 1;
        else
           shut_off_computer = 0;
    end

    always @(*) begin
        if (~arrived)
           keep_driving = ~gas_tank_empty;
        else
            keep_driving = 0;
    end

endmodule

5Always case

module top_module ( 
    input [2:0] sel, 
    input [3:0] data0,
    input [3:0] data1,
    input [3:0] data2,
    input [3:0] data3,
    input [3:0] data4,
    input [3:0] data5,
    output reg [3:0] out   );//

    always@(*) begin  // This is a combinational circuit
        case(sel)
            3'd0: out <= data0;
            3'd1: out <= data1;
            3'd2: out <= data2;
            3'd3: out <= data3;
            3'd4: out <= data4;
            3'd5: out <= data5;
            default: out <= 3'b0;
        endcase
    end

endmodule

6Always case2

最后一位高电平的索引，没有高电平也返回0

module top_module (
    input [3:0] in,
    output reg [1:0] pos  );
    always@(in)begin
        casex(in)
            4'bxxx1: pos <= 2'd0;
            4'bxx10: pos <= 2'd1;
            4'bx100: pos <= 2'd2;
            4'b1000: pos <= 2'd3;
            default: pos <= 2'd0;
        endcase
    end
endmodule

7Always casez

module top_module (
    input [7:0] in,
    output reg [2:0] pos );
    always@(in)begin
        casez(in)
            8'bzzzz_zzz1: pos <= 3'd0;
            8'bzzzz_zz10: pos <= 3'd1;
            8'bzzzz_z100: pos <= 3'd2;
            8'bzzzz_1000: pos <= 3'd3;
            8'bzzz1_0000: pos <= 3'd4;
            8'bzz10_0000: pos <= 3'd5;
            8'bz100_0000: pos <= 3'd6;
            8'b1000_0000: pos <= 3'd7;
            default: pos <= 3'd0;
        endcase
    end
endmodule

8Always nolatches

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up  ); 
    always@(scancode)begin
        case(scancode)
            16'he06b: {left, down, right, up} <= 4'b1000;
            16'he072: {left, down, right, up} <= 4'b0100;
            16'he074: {left, down, right, up} <= 4'b0010;
            16'he075: {left, down, right, up} <= 4'b0001;
            default: {left, down, right, up} <= 4'b0000;
        endcase
    end
endmodule