HDLBits 练习记录

近期进行了verilog编程语言的复习和回顾，顺便把网站上的题刷了一遍，个别题的答案解析也是参考网上的资源。虽然网上也有很多人做了详细的答案解析，有的博主讲解得详细透彻，比如：

https://blog.csdn.net/reborn_lee/category_9533452.html

https://blog.csdn.net/wangkai_2019/article/details/106100728#1.1%C2%A0Getting%20Started（Step%20one）

但是本人还是想简单总结、记录、分享一下自己的学习记录与心得，毕竟别人的东西是别人的。自己确定下来以后要往这个方向发展，就得一点一点的积累，先把简单的事情做好。给自己打点鸡血吧。哈哈！

希望能对初学者带来一定的帮助！

HDLBits 网站主要为练习Verilog 语言的使用和基本逻辑电路的设计。网站提供了在线编程环境，用户根据题目编写代码之后，直接可以运行仿真验证，观察时序，检查自己设计是否正确，对于初学者有一定的训练效果。

网址：HDLBits

举个状态机的例子吧！！

问题如下：

让你写程序，写完就可以提交综合仿真：

比如我的答案：

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    output walk_left,
    output walk_right); //  

    // parameter LEFT=0, RIGHT=1, ...
    parameter LEFT=0, RIGHT=1;
    reg state, next_state;

    always @(*) begin
        // State transition logic
        case(state)
            LEFT:begin
                case({bump_left,bump_right})
                    2'b00:next_state<=LEFT;
                    2'b01:next_state<=LEFT;
                    2'b10:next_state<=RIGHT;
                    2'b11:next_state=RIGHT;
                endcase
            end
            RIGHT:begin
                case({bump_left,bump_right})
                    2'b00:next_state<=RIGHT;
                    2'b01:next_state<=LEFT;
                    2'b10:next_state<=RIGHT;
                    2'b11:next_state=LEFT;
                endcase
            end
        endcase          
    end

    always @(posedge clk, posedge areset) begin
        // State flip-flops with asynchronous reset
        if(areset)begin
            state<=LEFT;
        end
        else begin
            state<=next_state;
        end
    end

    // Output logic
     assign walk_left = (state == LEFT);
     assign walk_right = (state == RIGHT);

endmodule

提交之后得到的仿真结果，错误会报错并提示错误信息。部分题也有编写程序的提示和提交正确后给出参考代码。

这个题的官方参考代码：

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	output walk_left,
	output walk_right
);

	// Give state names and assignments. I'm lazy, so I like to use decimal numbers.
	// It doesn't really matter what assignment is used, as long as they're unique.
	parameter WL=0, WR=1;
	reg state;
	reg next;
    
    
    // Combinational always block for state transition logic. Given the current state and inputs,
    // what should be next state be?
    // Combinational always block: Use blocking assignments.    
    always@(*) begin
		case (state)
			WL: next = bump_left  ? WR : WL;
			WR: next = bump_right ? WL : WR;
		endcase
    end
    
    
    // Combinational always block for state transition logic. Given the current state and inputs,
    // what should be next state be?
    // Combinational always block: Use blocking assignments.    
    always @(posedge clk, posedge areset) begin
		if (areset) state <= WL;
        else state <= next;
	end
		
		
	// Combinational output logic. In this problem, an assign statement are the simplest.
	// In more complex circuits, a combinational always block may be more suitable.		
	assign walk_left = (state==WL);
	assign walk_right = (state==WR);

	
endmodule

HDLBits网站题库主要分以下这几个主题，近期将简单总结分享一下。

这6个主题之下又可以分几个小节构成，每个小节针对一个知识内容进行针对性训练。如下图所示。

链接地址：

Problem sets

Getting Started

Verilog Language

Basics

Vectors

Modules: Hierarchy

Procedures

Procedures include always, initial, task, and function blocks. Procedures allow sequential statements (which cannot be used outside of a procedure) to be used to describe the behaviour of a circuit.

More Verilog Features

Circuits

Combinational Logic

Basic Gates

Multiplexers

Arithmetic Circuits

Karnaugh Map to Circuit

Sequential Logic

Latches and Flip-Flops

Counters

Shift Registers

More Circuits

Cellular automata

Finite State Machines

Building Larger Circuits

Counter with period 1000