Verilog 仿真文件对txt及bin文件的操作参考；

`timescale 1ns/1ps

module tb_top;
    parameter   P_REF_INDEX =  "../../../../../sim/0721/index.txt";
    parameter   P_REF_OMEGA =  "../../../../../sim/0721/omega_float.bin";
    parameter   P_REF_CCB   =  "../../../../../sim/0721/CCB_inv_All_bin.bin";
    parameter   P_REF_MATE  =  "../../../../../sim/0721/MATE_inv_fix_bin.bin";
    parameter   P_REF_GRID1 =  "../../../../../sim/0721/Grid1_inv_All_bin.bin";

    //signal define
    wire                                s_ETH_CLK                           ;
    wire                                s_USR_CLK                           ;
    reg                                 r_CLK_100                           ;
    reg                                 r_rst                               ;
    wire                                s_LED1                              ;

    reg                                 r_C0_SYS_CLK_P                      ;
    reg                                 r_C0_SYS_CLK_N                      ;
    wire                                s_C0_DDR4_ACT_N                     ;
    wire        [ 16:0]                 s_C0_DDR4_ADR                       ;
    wire        [  1:0]                 s_C0_DDR4_BA                        ;
    wire        [  0:0]                 s_C0_DDR4_BG                        ;
    wire        [  0:0]                 s_C0_DDR4_CKE                       ;
    wire        [  0:0]                 s_C0_DDR4_ODT                       ;
    wire        [  0:0]                 s_C0_DDR4_CS_N                      ;
    wire                                s_C0_DDR4_CK_T                      ;
    wire                                s_C0_DDR4_CK_C                      ;
    wire                                s_C0_DDR4_RESET_N                   ;
    wire        [  7:0]                 s_C0_DDR4_DM_DBI_N                  ;
    wire        [ 63:0]                 s_C0_DDR4_DQ                        ;
    wire        [  7:0]                 s_C0_DDR4_DQS_C                     ;
    wire        [  7:0]                 s_C0_DDR4_DQS_T                     ;
    wire                                s_C0_DDR4_INIT_DONE                 ;
    wire                                s_C0_DDR4_COMP_ERR                  ;

    reg         [ 31:0]                 r_SIMSTEP                           ;
    wire                                s_SIMSTEP_VLD                       ;

    integer                             cmd_line            = 1             ;//(i) Commond line
    integer                             file_line           = 1             ;//(i) File line
    reg         [1023:0]                MSG                 = 0             ;
    integer                             FOMEGA              = 0             ;
    integer                             FCCB                = 0             ;
    integer                             FZC                 = 0             ;
    integer                             FGRID1              = 0             ;
    integer                             FINDEX              = 0             ;
    reg                                 STR                 = 0             ;
    reg                                 ERR                 = 0             ;
    integer                             SEND_STATE          = 0             ;
    reg         [ 31:0]                 r_INIT_LINE         = 0             ;

    reg                                 r_LOAD_END                          ;

    reg                                 r_ETH_WR_START                      ;
    reg                                 r_ETH_WR_STOP                       ;
    reg         [ 31:0]                 r_ETH_WR_SEL                        ;
    reg         [ 31:0]                 r_ETH_WR_SADR                       ;
    reg                                 r_ETH_WR_DVLD                       ;
    reg         [63:0]                  r_ETH_WR_DATA                       ;
    reg         [ 7:0]                  r_ETH_WR_DATA_TMP       [7:0]       ;

    reg                                 r_ETH_RD_REQ                        ;
    reg         [ 31:0]                 r_ETH_RD_SADR                       ;
    reg         [ 31:0]                 r_ETH_RD_SEL                        ;
    reg         [ 31:0]                 r_ETH_RD_SIZE                       ;
    reg                                 r_ETH_RD_DVLD                       ;
    reg         [511:0]                 r_ETH_RD_DATA                       ;

//===============================================================================================
//output port