一收一发工程，工程下载在资源里https://download.csdn.net/download/tusiji5286/85169334。
顶层代码：

`timescale 1ns / 1ps
//
module TOP(
  input CLK_IN1_D_0_clk_n,
  input CLK_IN1_D_0_clk_p,
  input adc0_clk_0_clk_n,
  input adc0_clk_0_clk_p,
  input dac1_clk_0_clk_n,
  input dac1_clk_0_clk_p,
  input sysref_in_0_diff_n,
  input sysref_in_0_diff_p,
  input vin0_01_0_v_n,
  input vin0_01_0_v_p,
  output vout10_0_v_n,
  output vout10_0_v_p 
    );
wire clk_da,locked_da,clk_ad,locked_ad;
wire [31:0] douti,doutq;
wire [63:0] s10_axis_0_tdata;    
reg [12:0] cnt;    
always @(posedge clk_da or negedge locked_da) begin
if(!locked_da) cnt <= 13'd0;
else cnt <= cnt + 1'b1;
end
idata idata_i (
  .clka(clk_da),    // input wire clka
  .addra(cnt),  // input wire [12 : 0] addra
  .douta(douti)  // output wire [31 : 0] douta
);    
qdata qdata_i (
  .clka(clk_da),    // input wire clka
  .addra(cnt),  // input wire [12 : 0] addra
  .douta(doutq)  // output wire [31 : 0] douta
);    
assign s10_axis_0_tdata = {doutq[31:16],douti[31:16],doutq[15:0],douti[15:0]};    
wire [31:0]  m00_axis_0_tdata,m01_axis_0_tdata;   
RFSOC_1T1R_wrapper RFSOC_1T1R_wrapper_top
   (.CLK_IN1_D_0_clk_n (CLK_IN1_D_0_clk_n ),
    .CLK_IN1_D_0_clk_p (CLK_IN1_D_0_clk_p ),
    .adc0_clk_0_clk_n  (adc0_clk_0_clk_n  ),
    .adc0_clk_0_clk_p  (adc0_clk_0_clk_p  ),
    .clk_ad            (clk_ad            ),
    .clk_da            (clk_da            ),
    .dac1_clk_0_clk_n  (dac1_clk_0_clk_n  ),
    .dac1_clk_0_clk_p  (dac1_clk_0_clk_p  ),
    .locked_ad         (locked_ad         ),
    .locked_da         (locked_da         ),
    .m00_axis_0_tdata  (m00_axis_0_tdata  ),
    .m00_axis_0_tready (1'b1 ),
    .m00_axis_0_tvalid ( ),
    .m01_axis_0_tdata  (m01_axis_0_tdata  ),
    .m01_axis_0_tready (1'b1 ),
    .m01_axis_0_tvalid ( ),
    .s10_axis_0_tdata  (s10_axis_0_tdata  ),
    .s10_axis_0_tready ( ),
    .s10_axis_0_tvalid (1'b1 ),
    .sysref_in_0_diff_n(sysref_in_0_diff_n),
    .sysref_in_0_diff_p(sysref_in_0_diff_p),
    .vin0_01_0_v_n     (vin0_01_0_v_n     ),
    .vin0_01_0_v_p     (vin0_01_0_v_p     ),
    .vout10_0_v_n      (vout10_0_v_n      ),
    .vout10_0_v_p      (vout10_0_v_p      ));
   
wire [15:0] adi0,adi1,adq0,adq1;   
assign adi0 = m00_axis_0_tdata[15:0];   
assign adi1 = m00_axis_0_tdata[31:16];   
assign adq0 = m01_axis_0_tdata[15:0];   
assign adq1 = m01_axis_0_tdata[31:16];   
ila_adiq ila_adiq_top (
	.clk(clk_ad), // input wire clk
	.probe0({adq1,adq0,adi1,adi0}) // input wire [63:0] probe0
);      
endmodule

关于RF data converter的block design：

//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module RFSOC_1T1R_wrapper
   (CLK_IN1_D_0_clk_n,
    CLK_IN1_D_0_clk_p,
    adc0_clk_0_clk_n,
    adc0_clk_0_clk_p,
    clk_ad,
    clk_da,
    dac1_clk_0_clk_n,
    dac1_clk_0_clk_p,
    locked_ad,
    locked_da,
    m00_axis_0_tdata,
    m00_axis_0_tready,
    m00_axis_0_tvalid,
    m01_axis_0_tdata,
    m01_axis_0_tready,
    m01_axis_0_tvalid,
    s10_axis_0_tdata,
    s10_axis_0_tready,
    s10_axis_0_tvalid,
    sysref_in_0_diff_n,
    sysref_in_0_diff_p,
    vin0_01_0_v_n,
    vin0_01_0_v_p,
    vout10_0_v_n,
    vout10_0_v_p);
  input CLK_IN1_D_0_clk_n;
  input CLK_IN1_D_0_clk_p;
  input adc0_clk_0_clk_n;
  input adc0_clk_0_clk_p;
  output clk_ad;
  output clk_da;
  input dac1_clk_0_clk_n;
  input dac1_clk_0_clk_p;
  output locked_ad;
  output locked_da;
  output [31:0]m00_axis_0_tdata;
  input m00_axis_0_tready;
  output m00_axis_0_tvalid;
  output [31:0]m01_axis_0_tdata;
  input m01_axis_0_tready;
  output m01_axis_0_tvalid;
  input [63:0]s10_axis_0_tdata;
  output s10_axis_0_tready;
  input s10_axis_0_tvalid;
  input sysref_in_0_diff_n;
  input sysref_in_0_diff_p;
  input vin0_01_0_v_n;
  input vin0_01_0_v_p;
  output vout10_0_v_n;
  output vout10_0_v_p;

  wire CLK_IN1_D_0_clk_n;
  wire CLK_IN1_D_0_clk_p;
  wire adc0_clk_0_clk_n;
  wire adc0_clk_0_clk_p;
  wire clk_ad;
  wire clk_da;
  wire dac1_clk_0_clk_n;
  wire dac1_clk_0_clk_p;
  wire locked_ad;
  wire locked_da;
  wire [31:0]m00_axis_0_tdata;
  wire m00_axis_0_tready;
  wire m00_axis_0_tvalid;
  wire [31:0]m01_axis_0_tdata;
  wire m01_axis_0_tready;
  wire m01_axis_0_tvalid;
  wire [63:0]s10_axis_0_tdata;
  wire s10_axis_0_tready;
  wire s10_axis_0_tvalid;
  wire sysref_in_0_diff_n;
  wire sysref_in_0_diff_p;
  wire vin0_01_0_v_n;
  wire vin0_01_0_v_p;
  wire vout10_0_v_n;
  wire vout10_0_v_p;

  RFSOC_1T1R RFSOC_1T1R_i
       (.CLK_IN1_D_0_clk_n(CLK_IN1_D_0_clk_n),
        .CLK_IN1_D_0_clk_p(CLK_IN1_D_0_clk_p),
        .adc0_clk_0_clk_n(adc0_clk_0_clk_n),
        .adc0_clk_0_clk_p(adc0_clk_0_clk_p),
        .clk_ad(clk_ad),
        .clk_da(clk_da),
        .dac1_clk_0_clk_n(dac1_clk_0_clk_n),
        .dac1_clk_0_clk_p(dac1_clk_0_clk_p),
        .locked_ad(locked_ad),
        .locked_da(locked_da),
        .m00_axis_0_tdata(m00_axis_0_tdata),
        .m00_axis_0_tready(m00_axis_0_tready),
        .m00_axis_0_tvalid(m00_axis_0_tvalid),
        .m01_axis_0_tdata(m01_axis_0_tdata),
        .m01_axis_0_tready(m01_axis_0_tready),
        .m01_axis_0_tvalid(m01_axis_0_tvalid),
        .s10_axis_0_tdata(s10_axis_0_tdata),
        .s10_axis_0_tready(s10_axis_0_tready),
        .s10_axis_0_tvalid(s10_axis_0_tvalid),
        .sysref_in_0_diff_n(sysref_in_0_diff_n),
        .sysref_in_0_diff_p(sysref_in_0_diff_p),
        .vin0_01_0_v_n(vin0_01_0_v_n),
        .vin0_01_0_v_p(vin0_01_0_v_p),
        .vout10_0_v_n(vout10_0_v_n),
        .vout10_0_v_p(vout10_0_v_p));
endmodule

block design截图：