没有化简

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q
); 
    reg [511:0 ]q_l, q_r;
    assign q_l = {1'b0, q[511:1]};
    assign q_r = {q[510:0] , 1'b0};
    always @ (posedge clk)
        begin
            if (load)
                q <= data;
            else
                q <= (q_l&q& ~q_r) + (q_l & ~q & q_r) + (~q_l & q & q_r) + (~q_l & q & ~q_r) + (~q_l & ~q & q_r);
        end
endmodule